1. Field of the Invention
The present invention relates to a semiconductor device to be utilized for a memory cell of a nonvolatile memory and a method of manufacturing the semiconductor device.
2. Description of the Background Art
Examples of a semiconductor device to be utilized for a memory cell of a nonvolatile memory include an MONOS (Metal Oxide Nitride Oxide Semiconductor) transistor having a structure shown in FIG. 35. The MONOS transistor comprises a source region 111s and a drain region 111d which are formed in a semiconductor substrate 110, a gate insulating film 120 formed on the semiconductor substrate 110, and a gate electrode 130 formed on the gate insulating film 120.
The gate insulating film 120 is a laminated film (an ONO film) in which a silicon oxide film 121, a silicon nitride film 122 and a silicon oxide film 123 are sequentially provided. When the MONOS transistor is to be under a programming (writing) operation as a memory cell, proper voltages are applied to the semiconductor substrate 110, the gate electrode 130, the source region 111s and the drain region 111d, respectively, to trap electric charges CH1 such as electrons into the drain region 111d side in the silicon nitride film 122, for example. On the other hand, also when an erase operation is to be carried out, proper voltages are applied to respective portions to extract the trapped electric charges CH1.
In the case in which the electric charges CH1 are trapped, a change in a threshold voltage of the MONOS transistor is caused in contrast with in the case in which the electric charge CH1 is not trapped. By detecting the change in the threshold voltage, accordingly, it is decided whether 1-bit information is stored in a memory cell or not.
FIG. 36 is a top view showing a nonvolatile memory 101 constituted by a plurality of MONOS transistors illustrated in FIG. 35. In the nonvolatile memory 101, a source/drain region 111 including the source region 111s and the drain region 111d functions as a bit line and the gate electrode 130 functions as a word line. FIG. 35 shows a section of a memory cell CL portion in FIG. 36. The electric charges CH1 are trapped into a data storage region DR in the memory cell CL.
Both of FIGS. 37 and 38 are perspective views showing an example of a more specific structure of the nonvolatile memory 101 illustrated in FIG. 36. In a nonvolatile memory 101A shown in FIG. 37, an isolating region 140 is formed in portions of a source region 111s and a drain region 111d in adjacent memory cells CL. The source region 111s and the drain region 111d provided under the isolating region 140 continue between a plurality of memory cells and function as bit lines. Moreover, a gate insulating film 120 is divided for each memory cell in a direction of a channel length.
On the other hand, a nonvolatile memory 101B in FIG. 38 is not provided with a portion corresponding to the isolating region 140 in FIG. 37. Moreover, a gate insulating film 120 is provided continuously without a division for each memory cell in a direction of a channel length. In both of the nonvolatile memories 101A and 101B in FIGS. 37 and 38, an interlayer insulating film 150 provided on the MONOS transistor is illustrated transparently so as not to obstruct a lower structure thereof.
There are the following information about documents of the prior art related to the present application:
U.S. Pat. No. 5,768,192 specification (which will be hereinafter referred to as Patent Document 1);
Japanese Patent Application Laid-Open No. 2002-26149 (which will be hereinafter referred to as Patent Document 2);
Japanese Patent Application Laid-Open No. 5-75133 (1993) (which will be hereinafter referred to as Patent Document 3);
I. Bloom et al., “NROM anew non-volatile memory technology: from device to products”, (U.S.A.), Microelectronic Engineering 59(2001), pp.213-223 (which will be hereinafter referred to as Non-Patent Document 1);
B. Eitan et al., “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” (U.S.A.), SSDM1999 (which will be hereinafter referred to as Non-Patent Document 2);
E. Lusky et al., “Electron Discharge Model of Locally-Trapped Charge in Oxide-Nitride-Oxide (ONO) Gates for NROM Non-Volatile Semiconductor Memory Devices” (U.S.A.), SSDM2001 (which will be hereinafter referred to as Non-Patent Document 3);
T. Toyoshima et al., “0.1 μm Level Contact Hole Pattern Formation with KrF Lithography by Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS)” IEDM1998, p.333 (which will be hereinafter referred to as Non-Patent Document 4); and
J. De Blauwe et al., “Si-Dot Non-Volatile Memory Device” (U.S.A.), Extended Abstracts of the 2001 International Conference on Solid State Devices and Materials, Tokyo, 2001, pp.518-519 (which will be hereinafter referred to as Non-Patent Document 5).
As shown in FIG. 39, even if a channel length of an MONOS transistor to be a memory cell of a nonvolatile memory 101 (which has the same structure as that of the MONOS transistor in FIG. 35 and further comprises a sidewall insulating film 160) is reduced according to a progress of scaling (an advance in fineness of an element), an effective range of an electric field EF1 induced by trapped electric charges CH1 is not changed.
In the MONOS transistor, it is possible to trap electric charges into the source region 111s side as well as trapping of the electric charges CH1 into the drain region 111d side in the silicon nitride film 122. If the electric charges are trapped into each of the source/drain sides, one memory cell can hold 2-bit information.
In an MONOS transistor on the upper side of FIG. 40, electric charges are trapped into each of source/drain sides. Electric charges CH1 trapped into the drain region 111d side are indicated as bit1 and electric charges CH2 trapped into the source region 111s side are indicated as bit2.
Also in the case in which the electric charges are to be trapped into both of the source/drain sides, a channel length is reduced by the scaling as shown on the lower side of FIG. 40. In some cases in which the electric charges are to be trapped into each of the source/drain sides, the trapping of the electric charges CH2 is prevented by a repulsion of an electric field EF1 induced by the electric charges CH1 which are first trapped (This phenomenon is indicated as electric charges CH2a in FIG. 40). With a structure of a conventional semiconductor device, therefore, it is harder to hold multibit information in one memory cell when the scaling progresses.